LMDS Synthesizer Block Diagram
MC12022 MECL prescaler data sheet
Qualcomm Q3236 PLL data sheet (8/1997) (alternate copy here is shorter but more legible)
Qualcomm Synthesizer Products (4/2000, with some rendering problems)
Phase noise 26 GHz
Pictures and Brief Description
Revised Detailed Block Diagram
SNP2627 Block Diagram
SNP 520-series Data (another MicroSource YIG synthesizer with superior PN and tuning range)
Connection data
Wiring Reference for 25 pin D connector MSS2527-910-04 DC200393001 PIN REF Q3236 function(s) ____________________________________________ 1 d3 A3, SMODE 2 d1 A1 3 d8 M4, DBUS4, SEN\ 4 d6 M2, DBUS2 5 d4 M0, DBUS0 6 F LOCK 7 PWR BIT 8 +5 VDC, 700 mA 9 +15 VDC, 300 mA 10 -15 VDC, 45 mA 11 NC 12 NC 13 NC 14 d2 A2, M2 WR 15 d0 A0, FSELP 16 d7 M3, DBUS3 17 d5 M1, DBUS1 18 grnd 19 grnd 20 grnd 21 grnd 22 grnd 23 grnd 24 NC 25 NC
Programming notes
Calculate: N = Fmix / Fpfd where Fpfd is always 5 MHz (i.e., 960 MHz / 192) and Fmix is the desired YTO frequency Fyto minus 12480 MHz (960*13). Then, calculate M and A: M = int(N/10) - 1 A = N - 10(M+1) where the lower 5 bits of M are applied to these pins: M0: 5 M1: 17 M2: 4 M3: 16 M4: 3 and A is a 4-bit value applied to these pins: A0: 15 A1: 2 A2: 14 A3: 1 Notes:
- Register value constraints: A <= M+1, M = [1,31], N = [90,1295]
- Consequently, supported values of N range from 90 (M=8, A=0, Fyto=12930 MHz) to 329 (M=31, A=9, Fyto=14125 MHz)
- Qualcomm Q3236 PLL chip modes are direct parallel input with legacy Q3036 behavior
- Output frequency will be 2 * Fyto MHz unless you remove the doubler
Observed residual phase noise
